plat/qemu: move gicv2 codes to separate file

This file moves gicv2 codes to a new separate files, target is to add
gicv3 support later.

Signed-off-by: Hongbo Zhang <[email protected]>
Reviewed-by: Radoslaw Biernacki <[email protected]>
Tested-by: Radoslaw Biernacki <[email protected]>
Change-Id: I30eb1fda5ea5c2b35d79360c52f46601cbca1bcc

diff --git a/plat/qemu/include/platform_def.h b/plat/qemu/include/platform_def.h
index 2dd10ad8328e67bfe537e5182feb22806ae95d47..21492b40e399801180b0316653906f6f0d336225 100644 (file)
--- a/plat/qemu/include/platform_def.h
+++ b/plat/qemu/include/platform_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -219,6 +219,30 @@
 #define QEMU_IRQ_SEC_SGI_6             14
 #define QEMU_IRQ_SEC_SGI_7             15
 
+/******************************************************************************
+ * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0
+ * interrupts.
+ *****************************************************************************/
+#define PLATFORM_G1S_PROPS(grp)                                                \
+       INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY,    \
+                                          grp, GIC_INTR_CFG_EDGE),     \
+       INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY,    \
+                                          grp, GIC_INTR_CFG_EDGE),     \
+       INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY,    \
+                                          grp, GIC_INTR_CFG_EDGE),     \
+       INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY,    \
+                                          grp, GIC_INTR_CFG_EDGE),     \
+       INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY,    \
+                                          grp, GIC_INTR_CFG_EDGE),     \
+       INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY,    \
+                                          grp, GIC_INTR_CFG_EDGE),     \
+       INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY,    \
+                                          grp, GIC_INTR_CFG_EDGE),     \
+       INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY,    \
+                                          grp, GIC_INTR_CFG_EDGE)
+
+#define PLATFORM_G0_PROPS(grp)
+
 /*
  * DT related constants
  */

diff --git a/plat/qemu/platform.mk b/plat/qemu/platform.mk
index 85d83eaa78d9bb59a246d30f24b4d6ae535f3d09..2619587a38bf3fa67a0385e2cf532cbfcaabbfe0 100644 (file)
--- a/plat/qemu/platform.mk
+++ b/plat/qemu/platform.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -120,20 +120,22 @@ ifeq ($(add-lib-optee),yes)
 BL2_SOURCES            +=      lib/optee/optee_utils.c
 endif
 
+QEMU_GIC_SOURCES       :=      drivers/arm/gic/v2/gicv2_helpers.c      \
+                               drivers/arm/gic/v2/gicv2_main.c         \
+                               drivers/arm/gic/common/gic_common.c     \
+                               plat/common/plat_gicv2.c                \
+                               plat/qemu/qemu_gicv2.c
 
 ifeq (${ARM_ARCH_MAJOR},8)
 BL31_SOURCES           +=      lib/cpus/aarch64/aem_generic.S          \
                                lib/cpus/aarch64/cortex_a53.S           \
                                lib/cpus/aarch64/cortex_a57.S           \
-                               drivers/arm/gic/v2/gicv2_helpers.c      \
-                               drivers/arm/gic/v2/gicv2_main.c         \
-                               drivers/arm/gic/common/gic_common.c     \
-                               plat/common/plat_gicv2.c                \
                                plat/common/plat_psci_common.c          \
                                plat/qemu/qemu_pm.c                     \
                                plat/qemu/topology.c                    \
                                plat/qemu/aarch64/plat_helpers.S        \
-                               plat/qemu/qemu_bl31_setup.c
+                               plat/qemu/qemu_bl31_setup.c             \
+                               ${QEMU_GIC_SOURCES}
 endif
 
 # Add the build options to pack Trusted OS Extra1 and Trusted OS Extra2 images

diff --git a/plat/qemu/qemu_bl31_setup.c b/plat/qemu/qemu_bl31_setup.c
index 7453b89007c03d65733dab55b88ba258b7611320..4d36b039192a2ab9932fea46d4d5a0d8c2fdc51a 100644 (file)
--- a/plat/qemu/qemu_bl31_setup.c
+++ b/plat/qemu/qemu_bl31_setup.c
@@ -1,16 +1,12 @@
 /*
- * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include <assert.h>
 
-#include <platform_def.h>
-
 #include <common/bl_common.h>
-#include <drivers/arm/gic_common.h>
-#include <drivers/arm/gicv2.h>
 #include <plat/common/platform.h>
 
 #include "qemu_private.h"
@@ -73,49 +69,9 @@ void bl31_plat_arch_setup(void)
                              BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END);
 }
 
-/******************************************************************************
- * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0
- * interrupts.
- *****************************************************************************/
-#define PLATFORM_G1S_PROPS(grp)                                                \
-       INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY,    \
-                                          grp, GIC_INTR_CFG_EDGE),     \
-       INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY,    \
-                                          grp, GIC_INTR_CFG_EDGE),     \
-       INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY,    \
-                                          grp, GIC_INTR_CFG_EDGE),     \
-       INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY,    \
-                                          grp, GIC_INTR_CFG_EDGE),     \
-       INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY,    \
-                                          grp, GIC_INTR_CFG_EDGE),     \
-       INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY,    \
-                                          grp, GIC_INTR_CFG_EDGE),     \
-       INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY,    \
-                                          grp, GIC_INTR_CFG_EDGE),     \
-       INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY,    \
-                                          grp, GIC_INTR_CFG_EDGE)
-
-#define PLATFORM_G0_PROPS(grp)
-
-static const interrupt_prop_t qemu_interrupt_props[] = {
-       PLATFORM_G1S_PROPS(GICV2_INTR_GROUP0),
-       PLATFORM_G0_PROPS(GICV2_INTR_GROUP0)
-};
-
-static const struct gicv2_driver_data plat_gicv2_driver_data = {
-       .gicd_base = GICD_BASE,
-       .gicc_base = GICC_BASE,
-       .interrupt_props = qemu_interrupt_props,
-       .interrupt_props_num = ARRAY_SIZE(qemu_interrupt_props),
-};
-
 void bl31_platform_setup(void)
 {
-       /* Initialize the gic cpu and distributor interfaces */
-       gicv2_driver_init(&plat_gicv2_driver_data);
-       gicv2_distif_init();
-       gicv2_pcpu_distif_init();
-       gicv2_cpuif_enable();
+       plat_qemu_gic_init();
 }
 
 unsigned int plat_get_syscnt_freq2(void)

diff --git a/plat/qemu/qemu_gicv2.c b/plat/qemu/qemu_gicv2.c
new file mode 100644 (file)
index 0000000..fb56622
--- /dev/null
+++ b/plat/qemu/qemu_gicv2.c
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <drivers/arm/gicv2.h>
+#include <drivers/arm/gic_common.h>
+#include <platform_def.h>
+
+static const interrupt_prop_t qemu_interrupt_props[] = {
+       PLATFORM_G1S_PROPS(GICV2_INTR_GROUP0),
+       PLATFORM_G0_PROPS(GICV2_INTR_GROUP0)
+};
+
+static const struct gicv2_driver_data plat_gicv2_driver_data = {
+       .gicd_base = GICD_BASE,
+       .gicc_base = GICC_BASE,
+       .interrupt_props = qemu_interrupt_props,
+       .interrupt_props_num = ARRAY_SIZE(qemu_interrupt_props),
+};
+
+void plat_qemu_gic_init(void)
+{
+       /* Initialize the gic cpu and distributor interfaces */
+       gicv2_driver_init(&plat_gicv2_driver_data);
+       gicv2_distif_init();
+       gicv2_pcpu_distif_init();
+       gicv2_cpuif_enable();
+}
+
+void qemu_pwr_gic_on_finish(void)
+{
+       /* TODO: This setup is needed only after a cold boot */
+       gicv2_pcpu_distif_init();
+
+       /* Enable the gic cpu interface */
+       gicv2_cpuif_enable();
+}

diff --git a/plat/qemu/qemu_pm.c b/plat/qemu/qemu_pm.c
index 3249d6e27752bb3471f1c29e78989c6755ee2ac1..a199688dfac7d8275318ec4eb7b01f35b8c06155 100644 (file)
--- a/plat/qemu/qemu_pm.c
+++ b/plat/qemu/qemu_pm.c
@@ -1,19 +1,19 @@
 /*
- * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include <assert.h>
-
 #include <platform_def.h>
 
 #include <arch_helpers.h>
 #include <common/debug.h>
-#include <drivers/arm/gicv2.h>
 #include <lib/psci/psci.h>
 #include <plat/common/platform.h>
 
+#include "qemu_private.h"
+
 /*
  * The secure entry point to be used on warm reset.
  */
@@ -173,11 +173,7 @@ void qemu_pwr_domain_on_finish(const psci_power_state_t *target_state)
        assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] ==
                                        PLAT_LOCAL_STATE_OFF);
 
-       /* TODO: This setup is needed only after a cold boot */
-       gicv2_pcpu_distif_init();
-
-       /* Enable the gic cpu interface */
-       gicv2_cpuif_enable();
+       qemu_pwr_gic_on_finish();
 }
 
 /*******************************************************************************

diff --git a/plat/qemu/qemu_private.h b/plat/qemu/qemu_private.h
index 754831ab5af38caaf87d36e9d224c04a42ed4bc3..46b1ca1e9af83ba9e5666c2f547ce27f5352a9c6 100644 (file)
--- a/plat/qemu/qemu_private.h
+++ b/plat/qemu/qemu_private.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -33,4 +33,7 @@ int dt_add_psci_cpu_enable_methods(void *fdt);
 
 void qemu_console_init(void);
 
+void plat_qemu_gic_init(void);
+void qemu_pwr_gic_on_finish(void);
+
 #endif /* QEMU_PRIVATE_H */